Analog/digital conversion systems can be subdivided into two main categories according to the conversion principle on the basis of which they operate. The first category is based upon Nyquist analog/digital conversion systems, whereas the second category is based upon over-sampling analog/digital conversion systems.
A Nyquist analog/digital conversion system, as depicted in FIG. 1, is substantially composed of a continuous time anti-aliasing filter, a switched-capacitor channel filter operating at a frequency FS1, and a Nyquist analog/digital converter operating at a frequency FS2. The filters and the converter are connected in cascade. An over-sampling analog/digital conversion system is depicted in FIG. 2 and comprises a cascade connection of a continuous-time anti-aliasing filter, an over-sampling analog/digital converter operating at a frequency FS3, and a digital channel filter operating at a frequency FS4. In both systems, the signal VA should be sampled before being processed by the switched capacitor channel filter or by the over-sampling converter.
FIG. 3 shows the general circuit diagram of a commonly used sampling circuit. In particular, the sampling circuit comprises an input terminal at which an analog input voltage VA to be sampled is present, and an output terminal on which a corresponding sampled current is provided. The plates of a sampling capacitor are alternatively connected to the input or output nodes and to a ground node by four switches SW1, SW2, SW3 and SW4.
When the switches SW1 and SW3 are on and the switches SW2 and SW4 are off, the voltage VA is sampled and stored in the capacitor. In the opposite situation the sampled current is output, typically towards the virtual ground of an operational amplifier. The switches SW1, SW2, SW3 and SW4 are not ideal and have parasitic capacitances that introduce an undesired distortion. As a consequence, this significantly reduces the performances of the sampler.
To address this problem, in “Low-Distortion Switched-Capacitor Filter Design Techniques”, Kuang-Lu Lee and Robert G. Mayer, IEEE Journal of Solid-State Circuits, vol. sc-20, No. 6, December 1985, Section III B, pages 1103–1112, a technique of controlling the four switches with the control phases F1, F2, F1D, F2D shown in FIG. 4 has been proposed.
The high logic values of the control phases F1 and F2 are separated by a blanking time TD. This prevents short-circuits to ground. The control phases F1D and F2D are generated by delaying the control phases F1 and F2, respectively, by a time TR of a few nanoseconds. Moreover, the control phases F1D and F2 and the control phases F2D and F1 do not overlap one another.
According to the logic levels assumed by the control signals F1, F2, F1D and F2D, the sampling capacitor is connected alternately between the input node and the ground node, and between the latter and the output node. When the first and the fourth control signals F1, F1D assume a high logic level, the input voltage VA is sampled and the sample is stored in the sampling capacitor. When the second and the third control signals F2, F2D assume a high logic level, the sample of the input voltage VA stored in the sampling capacitor is transferred to the output node, and is sent to an operational amplifier.
As demonstrated in the above mentioned article, by using the structure shown in FIG. 3 and the control phases shown in FIG. 4, the distortion of the output signal is significantly reduced if the maximum frequency of the input voltage VA is smaller than 10 kHz.
However, at high frequencies, and in particular, at input frequencies greater than 100 kHz, the distortions are intolerable and the technique proposed in the above mentioned article is not sufficient. This is clearly demonstrated in the paper “A Cascaded Sigma-Delta Pipeline A/D Converter With 1.25 MHz Signal Bandwidth And 89 dB SNR”, T. L. Brooks et al., IEEE Journal Solid-State Circuits, vol. 32, No. 12, December 1997, Section IV B, pages 1896–1905.
According to the prior art, the sampling switch SW1 is usually implemented by a CMOS transfer-gate as shown in FIG. 5. As explained in the above mentioned article, this sampling switch has a series resistance that varies considerably as a function of the input voltage VA, as shown in FIG. 6. This causes strong distortions for input voltages VA at high frequency.
To overcome these drawbacks, the sampling circuit shown in FIG. 7, commonly known as “bootstrapped clock-boosted switch”, is proposed. In particular, the sampling circuit, bordered by a dashed rectangle, comprises an NMOS transistor M1. The current terminals of the NMOS transistor M1 are the input and the output nodes of the sampling circuit, and the control node of the NMOS transistor M1 is coupled to a boost capacitor CBOOST through a PMOS transistor controlled by the inverted replica {overscore (F1D)} of the control phase F1D.
A plate of the capacitor CBOOST is charged with the input voltage VA through a voltage buffer during the control phase F2D. This is while the other plate is connected to a ground node during the control phase F2D, and to the supply VCC during the control phase F1D.
When F2D is active, the gate of the switch M1 is connected to ground (M1 is off), the voltage V2 is null and the voltage V1 is the input voltage VA. When the control phase F1D is active (and thus F2D is inactive), the voltage V2 is the supply voltage, the voltage V1 isV1=VA+VCCand is applied to the gate node of the switch M1. Therefore, the switch M1 is on and its gate-source voltage equals the supply voltage VCC (boot-strap effect on the gate-source voltage).
The gate-source voltage of the switch M1 does not depend on the input voltage VA. Thus, the on-resistance RON of switch M1, which is a function of the difference between the gate-source voltage and its threshold voltage VT, is substantially constant.
A first limitation of the sampling circuit of FIG. 7 is that the bandwidth of the input voltage VA should be limited to frequencies which are much smaller than the sampling frequency. Otherwise, variations of the input voltage VA when the first control phase F1D is logically high and the second control signal F2D is logically low are too large. As a consequence, the gate-source voltage of the switch M1 could not be considered substantially equal to the supply voltage VCC. Therefore, all the advantages of the switching circuit described in the above mentioned article would be lost.
The sampling circuit thus needs a sampling frequency far greater than the Nyquist sampling frequency which results in a waste of power and a waste in silicon area. It should be remembered that, according to the well-known Nyquist theorem, no information is lost when sampling a signal VA if the sampling frequency is at least twice the maximum frequency of the signal VA to be sampled.
A second limitation is when the first control signal F1D is logically active, the voltages VG and V1 could exceed the maximum voltage allowed by the technology used for fabricating the circuit. For example, in a 0.5 μm technology, the maximum operating voltage that can be withstood by integrated devices is equivalent to 4.6 V, and typically the supply voltage VCC is 3.3 V.
Given that the maximum level VGMAX of the voltage VG (or V1) isVGMAX=VCC+VAMAXwhere VAMAX is the maximum voltage level of the input signal VA to be sampled, thenVAMAX≦1.3Vand this leads to a significant loss of signal/noise ratio of the A/D converter in which the sampling circuit is integrated.
A boosted sampling circuit that overcomes the drawbacks of the circuit of FIG. 7 is proposed in U.S. Pat. No. 6,518,901, as shown in FIG. 8. The '901 patent is incorporated herein by reference in its entirety, and is assigned to the current assignee of the present invention.
Like the circuit of FIG. 7, the switch M1 is on during the phase F1D and is off during the phase F2D. In contrast, when the control phase F2D is active, the capacitor CBOOST is connected between the supply VCC and ground. The plate connected to the transistor M3 is thus at the potentialVCC−VT.
When the control phase F1D is active, the other plate of the capacitor is charged with the input voltage VA making the voltage V1 equal toV1=VCC−VT+VA.
In so doing, the gate-source voltage of the switch M1 is constant and equal toVCC−VT.
The main difference between this switching circuit and the circuit of FIG. 7 is that the voltage VA is applied to a plate of the capacitor at the same time in which it is sampled by the switch M1. Therefore, the limitations on the frequency of the input signal are overcome.
Moreover, the maximum voltage VGMAX isVGMAX=VCC−VT+VAMAXthus, ifVGMAX≦4.6 V; VCC=3.3 V; VT=1.0 Vthe maximum level of the input voltage isVAMAX≦2.3 V.
Unfortunately, even this circuit is not very efficient with the most advanced technologies. In fact, in a 0.35 μm technology the maximum admissible voltage is 3.6 V and thus the maximum level of the input voltage now isVAMAX≦1.3 Vand the signal/noise ratio is consequently reduced.
U.S. Pat. No. 6,072,355 to J. L. Bledsoe discloses a bootstrap sample and hold circuit for acquiring and holding values of a high frequency analog input voltage. This circuit differs from the circuit of FIG. 8 because it has a node at a certain reference voltage that can never be the supply voltage. For this reason the circuit of the above mentioned patent needs an additional circuit for generating this reference voltage.
U.S. Pat. No. 6,323,697 to S. Pavan discloses a circuit that can be used as a low distortion sample and hold device of an input voltage. Even this circuit is affected by the drawback of requiring additional circuitry which is not present in the circuit of FIG. 8.